[IA64] install windows: multiple pagesize fix.

I think windows only use page size >= prefer page size (8K)
It is true in terms of boot windows
But install windows uses 4k page size.
This patch is intended to handle this case.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>

diff --git a/xen/arch/ia64/vmx/vmmu.c b/xen/arch/ia64/vmx/vmmu.c
index 2cb2db72c07fd9751955fc5e59e7e32915a3f1ea..d8022930f2961f1d6ce701824e50813c0d4ff3ab 100644 (file)
--- a/xen/arch/ia64/vmx/vmmu.c
+++ b/xen/arch/ia64/vmx/vmmu.c
@@ -375,7 +375,7 @@ IA64FAULT vmx_vcpu_itc_i(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa)
     }
 #endif //VTLB_DEBUG    
     pte &= ~PAGE_FLAGS_RV_MASK;
-    thash_purge_and_insert(vcpu, pte, itir, ifa);
+    thash_purge_and_insert(vcpu, pte, itir, ifa, ISIDE_TLB);
     return IA64_NO_FAULT;
 }
 
@@ -398,7 +398,7 @@ IA64FAULT vmx_vcpu_itc_d(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa)
     gpfn = (pte & _PAGE_PPN_MASK)>> PAGE_SHIFT;
     if (VMX_DOMAIN(vcpu) && __gpfn_is_io(vcpu->domain, gpfn))
         pte |= VTLB_PTE_IO;
-    thash_purge_and_insert(vcpu, pte, itir, ifa);
+    thash_purge_and_insert(vcpu, pte, itir, ifa, DSIDE_TLB);
     return IA64_NO_FAULT;
 
 }

diff --git a/xen/arch/ia64/vmx/vmx_process.c b/xen/arch/ia64/vmx/vmx_process.c
index 954c72180b4247c0800df7023a1a278395d9986f..e36d81820dfcae31b782bd952a96ed92e0c21e4b 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_process.c
+++ b/xen/arch/ia64/vmx/vmx_process.c
@@ -313,7 +313,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
                     ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST)) {
                     vcpu_get_rr(v, vadr, &rr);
                     itir = rr&(RR_RID_MASK | RR_PS_MASK);
-                    thash_purge_and_insert(v, pteval, itir , vadr);
+                    thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB);
                     return IA64_NO_FAULT;
                 }
                 if(vpsr.ic){
@@ -361,7 +361,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
                 if (pteval & _PAGE_P){
                     vcpu_get_rr(v, vadr, &rr);
                     itir = rr&(RR_RID_MASK | RR_PS_MASK);
-                    thash_purge_and_insert(v, pteval, itir , vadr);
+                    thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB);
                     return IA64_NO_FAULT;
                 }
                 if(!vpsr.ic){

diff --git a/xen/arch/ia64/vmx/vtlb.c b/xen/arch/ia64/vmx/vtlb.c
index 74ad2106a32bda18843dce5c0520db9182d5d01d..cfb84eaa3bf7846ae313631d48ec32a6eaf9d765 100644 (file)
--- a/xen/arch/ia64/vmx/vtlb.c
+++ b/xen/arch/ia64/vmx/vtlb.c
@@ -450,7 +450,7 @@ u64 translate_phy_pte(VCPU *v, u64 *pte, u64 itir, u64 va)
  * Purge overlap TCs and then insert the new entry to emulate itc ops.
  *    Notes: Only TC entry can purge and insert.
  */
-void thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa)
+void thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa, int type)
 {
     u64 ps;//, va;
     u64 phy_pte;
@@ -490,8 +490,14 @@ void thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa)
             }
         }
         else {
+            u64 psr;
+            phy_pte  &= ~PAGE_FLAGS_RV_MASK;
+            psr = ia64_clear_ic();
+            ia64_itc(type + 1, ifa, phy_pte, ps);
+            ia64_set_psr(psr);
+            ia64_srlz_i();
             // ps < mrr.ps, this is not supported
-            panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
+            // panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
         }
     }
     else{

diff --git a/xen/include/asm-ia64/vmmu.h b/xen/include/asm-ia64/vmmu.h
index f3698bf510a386aee31d334a3019a3bc978804bc..0f6d00a5bfed88705ed838a39397fbb206514476 100644 (file)
--- a/xen/include/asm-ia64/vmmu.h
+++ b/xen/include/asm-ia64/vmmu.h
@@ -270,7 +270,7 @@ extern thash_data_t *thash_find_next_overlap(thash_cb_t *hcb);
  *
  */
 extern void thash_purge_entries(struct vcpu *v, u64 va, u64 ps);
-extern void thash_purge_and_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa);
+extern void thash_purge_and_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa, int type);
 
 /*
  * Purge all TCs or VHPT entries including those in Hash table.